1. Field
Various exemplary embodiments of the present invention relate to a semiconductor design technology and, more particularly, to a semiconductor device including two or more circuits physically separated from each other, and an operating method thereof.
2. Description of the Related Art
A single semiconductor device may include multiple circuits that are physically separate and are capable of performing independent operations.
The semiconductor device circuits may share common signal transfer lines. The common signal transfer lines transfer signals throughout the device. These signals may include common command and data signals.
However, since the physical distance from the signal source (which may be internal or external) to each of the circuits may not be the same, the common signals often do not arrive at the circuits at the same time. In other words, the signal arrival times are not synchronized.
FIG. 1 is a block diagram illustrating a conventional semiconductor device.
Referring to FIG. 1, a first circuit 10 and a second circuit 20 are physically separated from each other in a conventional semiconductor device. The first circuit 10 includes an operation signal generation unit 14 and an internal circuit 12. The second circuit 20 includes an internal circuit 22. The internal circuits 12 and 22 of the first and second circuits 10 and 20 have separate paths A and B to the operation signal generation unit 14, and the distance a signal must travel is different. Particularly, path A between the internal circuit 12 and the operation signal generation unit 14, included in the first circuit 10, is shorter than the path B between the internal circuit 13 and the operation signal generation unit 14, as shown in FIG. 1.
The operation signal generation unit 14 transmits an operation signal OPSIG at the same time to the internal circuits 12 and 22 of the first and second circuits 10 and 20 through the paths A and B, which are different distances. But as discusses, the input timing of the operation signal OPSIG at each of the internal circuits 12 and 22 is different due to the differing lengths of paths A and B.
Because the internal circuits 12 and 22 have different signal input timing, this results in the operation timing of the internal circuits 12 and 22, in response to the operation signal OPSIG, being different. When the internal circuits 12 and 22 need to perform synchronous operations in response to the operation signal OPSIG, it is important to resolve this issue.
FIG. 2 is a block diagram illustrating another conventional semiconductor device.
Referring to conventional semiconductor device shown FIG. 2, it includes a delay section 216 with a shorter path A in to synchronize the operation timing of the internal circuits 12 and 22.
When the operation signal OPSIG is outputted from the operation signal generation unit 14 to the internal circuits 12 and 22 of the first and second circuits 10 and 20, the operation signal OPSIG is delayed by a delay section 216 in order to prevent timing issues between the internal circuits 12 and 22. The delay of the delay section 216 is designed in consideration of the travel time of the operation signal OPSIG on each of the paths A and B.
When the sum of the traveling time of the operation signal OPSIG on the path A and the delay of the delay section 216 is the same as the traveling time of the operation signal OPSIG on the path B, the input timings of the operation signal OPSIG at the internal circuits 12 and 22 are the same.
This is way the conventional art deals with this concern.
However, due to various factors, for example, unintended variation in the lengths of paths A and B that occur in mass-production, the delay of the delay section 216 may not synchronize the input timings of the operation signal OPSIG at the internal circuits 12 and 22, and this in turn may affect operation timing. To put it simply, there is room for improvement in the way that the conventional art is dealing with this concern.
If this concern is discovered after the mass-production of a batch of semiconductor devices, it is almost impossible to fix and it could result in the loss of substantial investment.
This timing concern not only applies to the situation that has been discussed, but may occur any time common signals are being sent to different locations. For example, when semiconductor devices have separate functional blocks or when multiple devices are grouped in a semiconductor system.